1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, it relates to a semiconductor integrated circuit comprising first, second and third wiring layers which are successively stacked on a semiconductor device group including a plurality of semiconductor devices having prescribed functions respectively.
2. Description of the Background Art
In relation to a general megabit-class semiconductor memory device, particularly a DRAM (dynamic random access memory), the mainstream is formed by a memory cell array architecture employing two layers of aluminum wires, as described in ESSCIRC Proceeding, September 1991, pp. 21 to 24.
A conventional semiconductor integrated circuit employing such two layers of aluminum wiring patterns is now described with reference to the drawings. FIG. 13 illustrates the structure on a chip of the conventional semiconductor integrated circuit.
Referring to FIG. 13, the semiconductor integrated circuit includes four memory cell array regions 31 which are arranged in two rows and two columns, and a peripheral circuit region 32 which is provided between the four memory cell array regions 31. Each memory cell array region 31 includes a plurality of subarrays 33 which are arranged in the row direction, a plurality of sense amplifier blocks 34 which are provided between and on both ends of the subarrays 33, a row decoder 35 which is arranged adjacently to the plurality of subarrays 33 and the plurality of sense amplifier blocks 34, and a column decoder 36 which is arranged adjacently to the innermost sense amplifier block 34.
Concrete structures of the subarrays 33 and the sense amplifier blocks 34 shown in FIG. 13 are now described. FIG. 14 illustrates the concrete structures of each subarray 33 and the sense amplifier blocks 34 shown in FIG. 13.
Referring to FIG. 14, each subarray 33 includes a plurality of memory cells MC, a plurality of bit lines BL and /BL (xe2x80x3/xe2x80x3stands for complementary signal wires), and a plurality of word lines WL. The subarray 33 has a folded bit line structure.
The memory cells MC are connected with corresponding ones of the bit lines BL and /BL and the word lines WL respectively. The bit lines BL and /BL are connected with sense amplifiers 34a. 
In the conventional DRAM, a plurality of semiconductor devices such as transistors and capacitors are formed on a silicon substrate, and a first high melting point metal wiring layer W, a second aluminum wiring layer Al1 and a third aluminum wiring layer Al2 are successively stacked thereon.
In the region shown in FIG. 14, the first high melting point metal wiring layer W is employed as the bit lines BL and /BL. The second aluminum wiring layer Al1 is employed as parts of the word lines WL. In more concrete terms, this layer Al1 is employed as shunts (pile drivers) for reducing the time constants of the word lines WL. The third aluminum wiring layer Al2 is employed as column selection lines CSL for transmitting an output signal of each column decoder 36 shown in FIG. 13.
The bit lines BL and /BL are formed by the high melting point metal wiring layer W as hereinabove described, for the following reason:
It is necessary to reduce power consumption by reducing the capacitances of the bit lines BL and /BL themselves, to ensure operating margins by increasing signal amplitudes read from the memory cells MC, and to reduce noises between the bit lines BL and /BL by reducing the capacitances across the same. Thus, it is necessary to reduce the thicknesses of the bit lines BL and /BL, which in turn tend to be increased in resistance. However, it is necessary to reduce the bit lines BL and /BL in resistance, in order to increase the speed of the DRAM. Therefore, the high melting point metal wiring layer W having a low resistance value is employed for the bit lines BL and /BL, in order to reduce the resistances thereof in addition to reduction in thickness. The high melting point metal wiring layer W is also adapted to prevent the material forming the bit lines BL and /BL from migration into the silicon substrate. While the high melting point metal has generally been prepared from tungsten silicide (WSi), a material having a lower resistance such as tungsten (W) or titanium silicide (TiSi) is recently employed for the purpose of reduction in resistance.
The structure in an area X of the peripheral circuit region 32 shown in FIG. 13 is now described in detail. FIG. 15 is an enlarged view showing respective regions on the semiconductor substrate in the area X shown in FIG. 13.
Referring to FIG. 15, the area X of the peripheral circuit region 32 includes bus regions BR, NMOS regions NR and PMOS regions PR. The bus, NMOS and PMOS regions BR, NR and PR are alternately set along the longer edges of the area X respectively.
The bus regions BR are provided thereon with bus wires for transmitting signals from peripheral circuits by the third aluminum wiring layer Al2, with no semiconductor devices such as NMOS and PMOS transistors. On the other hand, the NMOS regions NR are provided with NMOS transistors, and the PMOS regions BR are provided with PMOS transistors and the like. The NMOS and PMOS regions NR and PR are hereinafter defined as circuit regions CR.
The structure of the third aluminum wiring layer Al2 in the area X is now described in detail. FIG. 16 is an enlarged view showing the structure of the third aluminum wiring layer Al2 in the area X shown in FIG. 13.
Referring to FIG. 16, a plurality of bus signal wires BSL are arranged in each bus region BR. Two power supply wires Vcc and Vss are arranged in each circuit region CR. The respective wires are thereafter similarly repeated on the respective regions. The bus signal wires BSL and the power supply wires Vcc and Vss are formed by the third aluminum wiring layer Al2.
The semiconductor devices which are formed on each circuit region CR are supplied with power supply voltages Vcc and Vss by the set of power supply wires Vcc and Vss. In more concrete terms, the third aluminum wiring layer Al2 is connected with the second aluminum wiring layer Al1 via through holes, while the second aluminum wiring layer Al1 is connected with prescribed semiconductor devices which are formed on the circuit regions CR through contact holes. Namely, the second aluminum wiring layer Al1 is employed as local wires for connection with the semiconductor devices which are formed on the circuit regions CR. Also on the bus regions BR, the second aluminum wiring layer Al1 is employed as local wires, for connecting the bus signal wires BSL which are formed by the third aluminum wiring layer Al2 with prescribed semiconductor elements formed on the circuit regions CR.
In the conventional DRAM, as hereinabove described, the first high melting point metal wiring layer W, which is employed as the bit lines BL and /BL in the memory cell array regions 31, is hardly used in the peripheral circuit region 32. This is because the sheet resistance of the conventional high melting point metal wiring layer W which is made of tungsten silicide (WSi) is so high that the signal delay is too large for application to local wires for connecting the semiconductor devices provided on the circuit regions CR with each other.
Therefore, it is necessary to use the second aluminum wiring layer, portions of the third aluminum wiring layer provided on the circuit regions and the remaining portions thereof as the local wires, the power supply wires and the bus signal wires respectively as hereinabove described, and hence it is necessary to provide the bus regions which are provided with no semiconductor devices on the semiconductor substrate, in addition to the circuit regions. Consequently, high integration of the semiconductor integrated circuit cannot be attained.
In recent years, however, it is possible to employ a high melting point metal wiring layer having a small sheet resistance, which is prepared from a high melting point metal material such as tungsten (W) or titanium silicide (TiSi). When a high melting point metal wiring layer which is made of such a material is employed for the wires provided in the peripheral circuit region, it is possible to prevent the aforementioned problem of the signal delay. Therefore, it is possible to create a new layout utilizing a high melting point metal wiring layer, which has been employed only as the bit lines BL and /BL in general.
An object of the present invention is to provide a semiconductor integrated circuit which is easy to lay out and suitable for high integration.
Another object of the present invention is to provide a semiconductor integrated circuit in which a hierarchical power supply consisting of a plurality of power supply wires is easy to lay out.
Still another object of the present invention is to provide a semiconductor integrated circuit which can reduce wiring capacitances of main buses for peripheral circuits and increase the speed of signal transmission through the main buses.
A further object of the present is to provide a semiconductor integrated circuit which can reduce crosstalks in signal wires for peripheral circuits, thereby reducing noises of the signal wires.
A further object of the present invention is to provide a semiconductor integrated circuit which can prevent circuits provided therein from being latched up.
A semiconductor integrated circuit according to an aspect of the present invention includes a semiconductor device group, which is formed on a semiconductor substrate, including a plurality of semiconductor devices having prescribed functions respectively, a first wiring layer, which is stacked on the semiconductor device group, including local wires for connecting the semiconductor devices with each other, a second wiring layer which is stacked on the first wiring layer to extend in a first direction, and a third wiring layer which is stacked on the second wiring layer to extend in a second direction intersecting with the first direction.
Due to the aforementioned structure, the first wiring layer is employed as the local wires for connecting the semiconductor devices with each other. Further, the second and third wiring layers extend in the directions intersecting with each other, whereby an arbitrary wire of the second wiring layer necessarily intersects with that of the third wiring layer in a single portion. Therefore, it is possible to connect arbitrary wires of the second and third wiring layers with each other by connecting such intersections. Further, it is possible to connect the second wiring layer with arbitrary semiconductor devices through the first wiring layer serving as the local wires. Consequently, it is possible to arbitrarily lay out wires such as power supply wires and signal wires on the first and second wiring layers for simplifying the layout, while it is possible to highly integrate the semiconductor integrated circuit with no requirement for forming bus regions provided with no semiconductor devices on the semiconductor substrate.
Preferably, the second direction for the extension of the third wiring layer is along the longitudinal direction of the semiconductor device group and the third wiring layer includes main bus wires for the semiconductor device group, while the second wiring layer includes local bus wires for the semiconductor device group.
Due to the aforementioned structure, the main bus wires are formed along the longitudinal direction of the semiconductor device group, while the local bus wires are formed along the direction for intersecting with the main bus wires. Further, the second wiring layer is arranged between the first and second wiring layers, whereby the wiring capacitance of the second wiring layer is increased and that of the third wiring layer is reduced. Therefore, it is possible to transmit signals at a high speed through the main bus wires having small wiring capacitances.
Preferably, the second wiring layer includes hierarchical power supply wires for supplying hierarchical power supply voltages to the semiconductor device group. Therefore, the second wiring layer can be employed as the hierarchical wires for supplying hierarchical power supply voltages to the semiconductor device group, whereby the hierarchical power supply wires are easy to lay out.
Preferably, the second wiring layer includes the power supply wires for supplying power supply voltages to the semiconductor device group and the third wiring layer includes signal wires for inputting/outputting prescribed signals in/from the semiconductor device group, while the power supply wires are arranged to cover the signal wires. Thus, the second wiring layer serving as the power supply wires is arranged to cover the third wiring layer serving as the signal wires, whereby the second wiring layer effectively serves as a shielding layer. Consequently, crosstalks between the first and third wiring layers are reduced, and it is possible to reduce noises of the signal wires formed by the third wiring layer.
Preferably, the semiconductor integrated circuit has connecting portions which are formed by partially hollowing the second wiring layer serving as the power supply wires, for connecting at least one of the first wiring layer and the semiconductor device group with the third wiring layer. Consequently, it is possible to readily connect the first wiring layer or the semiconductor device group with the third wiring layer also when the power supply wires are increased in width, whereby the layout is simplified.
Preferably, the semiconductor device group includes semiconductor devices of a first conductivity group and those of a second conductivity group which is different from the first conductivity group, while the semiconductor substrate includes a first region provided with the first conductivity type semiconductor devices, a second region, which is arranged adjacently to the first region, provided with the second conductivity type semiconductor devices, a third region, which is arranged adjacently to the second region, provided with the second conductivity type semiconductor devices, and a fourth region, which is arranged adjacently to the third region, provided with the first conductivity type semiconductor devices.
Due to the aforementioned structure, the second and third regions which are provided with the second conductivity type semiconductor devices are arranged between the first and second regions which are provided with the first conductivity type semiconductor devices, whereby the space between the first and fourth regions is widened and it is possible to prevent circuits provided on the respective regions from being latched up.
Preferably, the second wiring layer supplies a set of hierarchical power supply voltages to the first or fourth region. Therefore, the number of the power supply wires is reduced and the second wiring layer is easy to lay out.
Preferably, the semiconductor device group includes semiconductor devices of a first conductivity type and those of a second conductivity type which is different from the first conductivity type, and the semiconductor substrate includes a plurality of circuit regions including a first region provided with the first conductivity type semiconductor devices and a second region, which is arranged adjacently to the first region, provided with the second conductivity type semiconductor devices, while one of the plurality of circuit regions includes a switching device forming region forming a switching device for generating a set of hierarchical power supply voltages, and the third wiring layer includes a hierarchical power supply wire for supplying the set of hierarchical power supply voltages generated from the one of the circuit regions to the remaining circuit regions.
Due to the aforementioned structure, one of the plurality of circuit regions is provided with the switching device region forming the switching device for generating the set of hierarchical power supply voltages so that the set of hierarchical power supply voltages as generated are supplied to the remaining circuit regions, whereby the area of the switching device region can be reduced and high integration of the semiconductor integrated circuit can be attained.
A semiconductor integrated device according to another aspect of the present invention includes a memory cell array including a plurality of memory cells which are arranged in row and column directions respectively, a peripheral semiconductor device group including a plurality of semiconductor devices, which are arranged around the memory cell array, having prescribed functions respectively, a first wiring layer, which is stacked on the memory cell array and the peripheral semiconductor device group, including bit lines connected with the memory cells and local wires connected with the semiconductor devices respectively, a second wiring layer, which is stacked on the first wiring layer, including main bus wires extending in a first direction, and a third wiring layer, which is stacked on the second wiring layer, including local bus wires extending in a second direction intersecting with the first direction.
Due to the aforementioned structure, the first wiring layer can be employed as the bit lines connected to the memory cells and the local wires connecting the semiconductor devices with each other. Further, the second and third wiring layers extend to intersect with each other, whereby an arbitrary wire of the second wiring layer necessarily intersects with that of the third wiring layer in a single portion. Therefore, it is possible to connect arbitrary wires of the second and third wiring layers with each other by connecting such intersections, while it is possible to connect the peripheral semiconductor device group with the local bus wires and the main bus wires by connecting the first and second wiring layers with each other. Consequently, it is possible to readily connect an arbitrary wire of the third wiring layer with the peripheral semiconductor device group for simplifying the layout, while it is possible to highly integrate the semiconductor integrated circuit with no requirement for forming bus regions provided with no semiconductor devices in the region provided with the peripheral semiconductor device group.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.